Q.No.1

The primary advantage of hardwired control unit over microprogrammed control unit is:

Q.No.2

Pipelining in VHDL allows for:

Q.No.3

In horizontal microinstruction format:

Q.No.4

Which of the following is NOT a typical field in a microinstruction format?

Q.No.5

The primary difference between RISC and CISC architectures is:

Q.No.6

A hazard in pipelining that occurs when an instruction depends on the result of a previous instruction still in the pipeline is called:

Q.No.7

The primary advantage of a multilevel cache hierarchy is:

Q.No.8

Cache coherence is an issue in:

Q.No.9

The hit ratio in cache memory is:

Q.No.10

Memory-mapped I/O means:


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